IEEE Transactions on Computers

IEEE Transactions on Computers (TC) is a monthly publication that publishes research in such areas as computer organizations and architectures, digital devices, operating systems, and new and important applications and trends.


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From the March 2019 issue

ASAP: Accelerated Short-Read Alignment on Programmable Hardware

By Subho Sankar Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Zbigniew T. Kalbarczyk, Deming Chen, Steven S. Lumetta, and Ravishankar K. Iyer

Featured article thumbnail image The proliferation of high-throughput sequencing machines ensures rapid generation of up to billions of short nucleotide fragments in a short period of time. This massive amount of sequence data can quickly overwhelm today's storage and compute infrastructure. This paper explores the use of hardware acceleration to significantly improve the runtime of short-read alignment, a crucial step in preprocessing sequenced genomes. We focus on the Levenshtein distance (edit-distance) computation kernel and propose the ASAP accelerator, which utilizes the intrinsic delay of circuits for edit-distance computation elements as a proxy for computation. Our design is implemented on an Xilinx Virtex 7 FPGA in an IBM POWER8 system that uses the CAPI interface for cache coherence across the CPU and FPGA. Our design is 200× faster than an equivalent Smith-Waterman-C implementation of the kernel running on the host processor, 40−60× faster than an equivalent Landau-Vishkin-C++ implementation of the kernel running on the IBM Power8 host processor, and 2× faster for an end-to-end alignment tool for 120-150 base-pair short-read sequences. Further the design represents a 3760× improvement over the CPU in performance/Watt terms.

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