IEEE Computer Architecture Letters
IEEE Computer Architecture Letters (CAL) is a semi-annual forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers. Submissions are welcomed on any topic in computer architecture.
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From the July-December 2017 issue
Resistive Address Decoder
By Leonid Yavits, Uri Weiser, and Ran Ginosar
Hardwired dynamic NAND address decoders are widely used in random access memories to decode parts of the address. Replacing wires by resistive elements allows storing and reprogramming the addresses and matching them to an input address. The resistive address decoder thus becomes a content addressable memory, while the read latency and dynamic energy remain almost identical to those of a hardwired address decoder. One application of the resistive address decoder is a fully associative TLB with read latency and energy consumption similar to those of a one-way associative TLB. Another application is a many-way associative cache with read latency and energy consumption similar to those of a direct mapped one. A third application is elimination of physical addressing and using virtual addresses throughout the entire memory hierarchy by introducing the resistive address decoder into the main memory.
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